TL;DR: Cardano is highlighting a 12-team Catalyst pilot in which much of the grant funding depends on real adoption rather than merely launching a project.

Crypto grant programmes have a familiar problem: it’s easier to count funded ideas than products anyone actually uses. Cardano’s Project Catalyst has been trying a different approach with its 2026 pilot cohort, which is now being highlighted again by the ecosystem.

The original selection announcement came on September 24. Twelve teams were chosen from 117 applications, covering areas including stablecoin payments, lending, programmable tokens, identity and supply-chain applications. The pool was designed around roughly two million ADA in grant funding.

The more interesting detail is how teams get paid. Catalyst says 40% of an approved grant is released after onboarding, while the rest is linked to adoption targets and continued use. That asks recipients to demonstrate something after deployment, rather than treating a completed build as the final measure of success.

The programme also involved 52 active community curators, with specialist reviewers examining the business and technical case for applications.

None of that proves that the selected projects will succeed. There is a difference between promising measurable use and demonstrating it on-chain, and the pilot will ultimately be judged on the latter.

Still, the funding model gives Cardano a concrete experiment to watch: can distributing ADA on the basis of usage deliver better outcomes than the traditional grant cycle?

Written by the News Desk and edited by Samuel Rae.

I recently got the Amazon Christmas toy book in the mail, and it is definitely the modern version of the Sears Christmas Wish Book for last century’s youth. Or at least the majority of last century’s youth. For the true hacker, we had a different set of wishes. Recently, I found something I’ve clung to for over 50 years: the 1975 “The Age of Altair” catalog from MITS. Now that was a wish book!

The poor thing has been dragged around for decades and, I’m sad to say, it looks it. It isn’t totally trash, but I decided I should scan it. Then I realized that Bitsavers has already done it for me and with a much nicer copy, too. The images in this post are from their scan instead.

About the Altair

If your first computer ran Windows, you might not get the significance of the Altair. Back in 1974, the idea of having your own computer was practically ludicrous. Sure, Radio Electronics had published plans for the Mark 8 in July of that year. But it used an anemic 8008 CPU, and it wasn’t easy to get all the parts you’d need to build one. Other limited computers, like the Kenbak-1 or the occasional surplus minicomputer, ended up in personal hands. But you couldn’t just decide you wanted a real computer, plunk down some money, and have one delivered unless you had extremely deep pockets.

To stay on magazine stands longer, old print mags would come out earlier than their cover date suggested. The January 1975 Popular Electronics arrived, actually, in December of 1974 — just in time for the holidays. It showed a computer you could buy as a kit or assembled: the Altair 8800. Many of us were mesmerized by the idea of owning an actual useful computer.

Reality Check

Of course, the problem is, it wasn’t actually a useful computer. All by itself, it was a bunch of switches and LEDs with a CPU. You’d need memory, and even a little was super expensive. But it was still cheaper than anything else. Want a terminal and enough memory to run BASIC? That’s going to be even more.

In those days, magazines had “bingo cards.” Each ad had a number, and if you wanted more information, you circled that number on the card and mailed it to the magazine. A while later, you’d be rewarded with mail from the company in question. I have no idea how many of the “Age of Altair” catalogs were sent, but I know I got one.

The machine on the cover didn’t look much like the machine in the magazine. The story is that the original machine was sent to the magazine for photography and was lost in the return shipping. But either way, it looked like a small minicomputer of the era.

Micro

The catalog notes a cycle time of two microseconds, or about 500 kHz. That’s a little misleading. The CPU actually ran at 2 MHz, but each instruction took multiple clock periods, and some instructions required several machine cycles. Even a simple NOP took two microseconds, while more complex instructions could take considerably longer. It wasn’t a speed demon.

One nice thing about the Altair is that it had a card cage, and you could plug in whatever you wanted with what would later be called the S-100 bus. Of course, to save money, you might not get all the card guides and connectors.

If you had deep pockets, you could get fast static memory. This would cost more and provide less memory, but the chips stored bits in flip-flops, and it was fast. Or you could opt for more dynamic memory, which stored data in tiny capacitors on its memory chips. The downside is that the memory had to periodically refresh itself, stealing cycles away from the already slow CPU.

Down with Switches

Naturally, you didn’t want to flip switches all the time. MITS offered the Comter 256 terminal. It had 256 bytes of its own storage and a whopping 32-character display. It even had holes to stick your phone in, if you wanted to talk to a remote computer.

This was, of course, not very practical. Your best bet was a TeleType. The TeleType Model 33 had a printer and a keyboard. The ASR variant had a paper tape reader and punch, too. Mass storage and a printer that operated at 10 characters per second. No screen, though. Everything you did was on paper. And it was pricey, too.

Software

The catalog offered a 4K and 8K BASIC along with “Extended” BASIC, which needed 12K but got you double precision math, PRINT USING, and disk I/O. There was also a single page of 8080 instructions in binary. I remember fixating on that page, trying to understand how you’d program this machine. There was a lot of missing detail.

Pricing

For as cheap as these were compared to the alternatives, they were still out of reach for many people, especially a kid. The computer itself was just a bit over $600 unless you wanted to build it yourself. Then you could save just under $200.

You couldn’t do anything without memory, though. A board that could hold 1 kB of static RAM (but only came with 256 bytes) was $134 assembled, plus $61 for every 256 bytes after that. If you wanted the board fully loaded, they discounted that to $209. The slower 4 kB dynamic RAM board was a cool $338. If you didn’t have paper tape, you probably wanted the interface to load and save programs from cassette. That was another $174.

Wanted something with a keyboard? The Comter terminal was $885, but for $35 more, you could get one that would also work with your cassette recorder to save and load things. Or opt for the TeleType for $1,500. You might be tempted by the 88-VLCT (the “low cost terminal”) at only $169. But if you saw it, it only had seven numeric keys (for octal) and two other buttons.

That’s not all. Those terminals had to plug into something. That board would run you around $140, depending on which variant you wanted. Even something like a real-time clock was an extra purchase.

The base computer price had four available slots, one of which held the CPU. So if you had a CPU, two memory cards, and a serial I/O card, you were full unless you bought more slots. To make it easier, you could buy a bundle. The cheapest was just shy of $3,000.

Perspective

I know. It is easy enough to spend $3,000 on a state-of-the-art computer today and, at the time, this was pretty state-of-the-art. But in today’s dollars, that’s about $19,000. A new car was about $5,000, and $3,000 would get you a very nice used car. An average home ran about $42,000, and  $3,000 would be a hefty part of a down payment. The median income in 1975? Under $14,000.

Still, these were the first real computers you could at least imagine buying. It wouldn’t be long before the prices of even better machines dropped considerably.

I wasn’t the only one who wanted one of these machines. I conspired with friends to pool money to get one, but we never managed it. I pored over machine code listings in later magazines and the instruction reference in the catalog, trying to puzzle it out. I finally did. In those days, you couldn’t just download the manuals or watch a video about it.

Then again, the value of an original working Altair 8800 today makes it, again, out of reach for most of us. There are always faithful recreations. Or even less-than-faithful ones. I have plenty of these recreations and simulations now, but I still have kept the catalog I pored over so many years ago.

TL;DR: Cardano is highlighting a 12-team Catalyst pilot in which much of the grant funding depends on real adoption rather than merely launching a project.

Crypto grant programmes have a familiar problem: it’s easier to count funded ideas than products anyone actually uses. Cardano’s Project Catalyst has been trying a different approach with its 2026 pilot cohort, which is now being highlighted again by the ecosystem.

The original selection announcement came on September 24. Twelve teams were chosen from 117 applications, covering areas including stablecoin payments, lending, programmable tokens, identity and supply-chain applications. The pool was designed around roughly two million ADA in grant funding.

The more interesting detail is how teams get paid. Catalyst says 40% of an approved grant is released after onboarding, while the rest is linked to adoption targets and continued use. That asks recipients to demonstrate something after deployment, rather than treating a completed build as the final measure of success.

The programme also involved 52 active community curators, with specialist reviewers examining the business and technical case for applications.

None of that proves that the selected projects will succeed. There is a difference between promising measurable use and demonstrating it on-chain, and the pilot will ultimately be judged on the latter.

Still, the funding model gives Cardano a concrete experiment to watch: can distributing ADA on the basis of usage deliver better outcomes than the traditional grant cycle?

Written by the News Desk and edited by Samuel Rae.

When you first learn to program, memory seems pretty straightforward. You have a bunch of bytes, each with an address. If you want to read or write something, you specify the address, and the computer goes to that place and does your bidding. Sure, some addresses might be reserved for hardware or the operating system, but the general idea is simple: memory is a big array of bytes.

Just like we pretend that a wire is a perfect conductor, the big array of memory model used to be a slight twisting of the truth. On a modern computer, however, it is almost entirely a lie. The address you use probably isn’t a physical address. The data you read might not come from RAM at all. Even if it does, it might be sitting in one of several caches. And if you follow the rabbit hole far enough, you discover that your SSD is arguably just another level in the memory hierarchy.

The Need For Speed

The fundamental problem is that processors have gotten much faster than memory. A modern processor can execute several instructions per clock cycle, but accessing ordinary DRAM can take hundreds of cycles. If the processor had to wait for RAM every time it needed data, much of that impressive computing power would go to waste.

The solution is caching. Keep copies of frequently used data in smaller, faster memories closer to the processor. Most modern desktop processors have at least three levels of cache. The L1 cache is tiny but extremely fast, and often split between instructions and data. L2 is larger and somewhat slower, while L3 is even larger and usually slower as well.

Things get interesting with multiple cores, as is often the case these days. Typically, each core has its own L1 and L2 caches, while several cores share an L3 cache. But that’s not universal. Some processors share L2 caches between cores. Others have multiple L3 caches, each serving a group of cores. The exact arrangement depends on the processor architecture.

One important detail: caches don’t generally work byte by byte. They transfer and track blocks called cache lines, commonly 64 bytes on modern desktop processors. If you read one byte that isn’t cached, the processor generally fetches the entire line containing that byte.

This is why sequential memory access is often much faster than random access. If you read the next byte, there’s a good chance it’s already in the cache. Hardware prefetchers may even anticipate what you’ll need next.

But there can be problems. Imagine two cores modifying completely different variables. If those variables happen to occupy the same cache line, the cores may repeatedly invalidate each other’s copies, wasting time even though they aren’t logically sharing data.

Protocols such as MESI keep the caches coherent, coordinating which core owns a line and which copies are valid. MESI is an acronym for cache line states: modified, exclusive, shared, or invalid. Memory systems must figure out how to keep caches in sync. But coherence doesn’t eliminate the need for synchronization or memory-ordering rules in multithreaded programs. The point is that even our simple byte-addressed memory is secretly operating in larger chunks.

The Address Isn’t Real, Either

So far, we’ve assumed that the address you supply identifies a location in RAM. Usually, it doesn’t. Modern operating systems use virtual memory. Your program sees a virtual address space that the operating system and processor cooperate to map onto physical memory.

The memory management unit, or MMU, translates virtual addresses into physical addresses, typically using page tables. This lets different programs use identical virtual addresses without interfering with one another. It also provides memory protection and allows physical pages to be shared.
Of course, translating addresses takes time. So we add another cache.

The translation lookaside buffer, or TLB, remembers recently used address translations. A TLB hit avoids a potentially expensive page-table walk. Some processors even have multiple levels of TLBs. Unlike the ordinary CPU cache, which generally operates on cache lines, virtual memory usually works with pages, often 4 KB, although larger pages are also supported.

Notice what’s happening. We have caches for data, caches for instructions, and caches for the information needed to locate the data and instructions.
The simple act of reading a variable has become surprisingly complicated.

Not All RAM Is Created Equal

Even if we get through the caches and finally reach RAM, things aren’t necessarily simple. On systems with multiple processors or certain multicore arrangements, memory access can be non-uniform. This is called NUMA, or Non-Uniform Memory Access.

A processor may have relatively fast access to memory attached to its own NUMA node, while accessing memory associated with another node requires crossing an interconnect. Both locations are ordinary RAM, and both may appear in the same address space, but the access times and available bandwidth can differ.

The operating system tries to place memory near the processors using it. Moving a thread to another CPU can therefore change its memory performance, even though the program’s addresses haven’t changed.

And NUMA isn’t limited to traditional multiprocessor servers. Modern systems with chiplets, heterogeneous memory, and technologies such as CXL are making memory topology increasingly interesting.

What If It Isn’t In Memory?

Virtual memory has another trick. A virtual page doesn’t necessarily have to be backed by physical RAM at the moment you access it.

When a program accesses a page that isn’t currently mapped in a usable way, the processor generates a page fault. The operating system decides what to do. Sometimes it simply allocates a fresh page. Sometimes it retrieves data from an executable or memory-mapped file. Other times, the page was moved out of RAM to swap space and must be retrieved. Note that things like executable data are generally immutable, so most operating systems won’t swap them out. They simply trash them and know they can reload the same page later when needed.

This means your program can address data that isn’t presently in physical memory. Naturally, accessing an SSD is much slower than accessing RAM, so excessive swapping can bring a computer to its knees.

Virtual memory doesn’t actually require swapping, though. Address translation and protection are useful even on systems that never move pages to disk.

Your SSD Is Memory, Too

Suppose your program reads a file. You might imagine that the operating system sends a request to the SSD and waits for the data. But if the file was recently accessed, the data may already be in RAM.

Operating systems maintain a filesystem page cache, keeping frequently or recently accessed file data in memory. Writes may also be buffered in RAM before eventually reaching persistent storage.

This makes RAM act like a cache for secondary storage, much as L3 acts like a cache for RAM.

The analogy isn’t perfect. RAM is also the primary working storage for running programs, and anonymous memory isn’t necessarily a copy of anything on disk. But the general hierarchy is clear: registers, CPU caches, RAM, and persistent storage provide progressively different tradeoffs between speed, capacity, and cost.

Even SSDs have their own caches and address translations. Their flash translation layers map logical block addresses onto physical flash locations, hiding wear leveling and garbage collection from the host. Apparently, nobody wants to tell the truth about addresses.

Compressing The Middle

But what if we could make RAM effectively larger without adding more? Compression offers another way to complicate our memory hierarchy. Instead of immediately moving an infrequently used page to disk, why not compress it and keep it in RAM?

Linux has two well-known mechanisms for doing this: zram and zswap. Zram creates a compressed block device in RAM. It’s commonly used as a swap device, allowing pages to be stored in compressed form rather than written to physical storage.

Zswap, on the other hand, is a compressed cache in front of a swap device. When Linux decides to swap out a page, zswap attempts to compress and retain it in RAM. If necessary, pages can eventually be evicted to the backing swap device.

Both trade processor time for memory capacity and reduced storage I/O. Decompressing a page costs CPU cycles, but that can be considerably cheaper than retrieving it from an SSD.

There’s a catch, though. These mechanisms operate through the swap subsystem. When a compressed page is needed again, it must be decompressed into an ordinary page before the program can access it. That means page faults, memory management overhead, and moving data around. But what if compressed memory could behave more like ordinary RAM?

Meta Wants To Change The Rules

That’s the idea behind CRAM, or Compressed RAM, a project presented by Meta’s Gregory Price at the October 2026 Linux Plumbers Conference.

Rather than treating compressed memory as a conventional swap device, CRAM proposes exposing it through a special NUMA node. Linux can then use existing memory-management mechanisms to move pages between ordinary DRAM and compressed memory. The most interesting part is the hardware-assisted compression and decompression, which allows access at much finer granularity than conventional page-oriented compressed swap.

The developers report impressive benchmark results, including read performance that approaches ordinary DRAM in some tests and dramatic improvements over zram for selected workloads.

That doesn’t mean compression has suddenly become free. Writes, compression ratios, hardware requirements, and managing incompressible data all matter. CRAM is still developmental work, not ready for everyday use.

But it illustrates where the memory hierarchy is heading. Instead of simply deciding whether a page is in RAM or on disk, the operating system may choose among ordinary RAM, compressed memory, slower memory tiers, and secondary storage.

The Illusion Is The Feature

Most programmers don’t need to think about any of this most of the time. That’s the point of an abstraction. But when performance matters, the illusion starts to leak. Sequential access can beat random access by enormous margins. Two threads modifying unrelated variables can fight over cache lines. Moving a process between CPUs can change its memory latency. A page that looks like ordinary memory might actually require decompression or a trip to an SSD.

On smaller embedded systems, of course, the picture may be very different. Without an MMU or elaborate caches, memory can look much more like the simple physical address space we learned about in the first place.

We started with an array of bytes. We ended up with a hierarchy of caches, translation tables, NUMA nodes, compressed memory pools, and persistent storage devices, all cooperating to maintain that simple illusion. Amazing how complicated something so simple can be.

Seattle startup Meadow AI has raised $7 million in new funding to scale its AI-powered operational software for physical retailers and restaurants.

The seed round was led by Ulu Ventures, with participation from York IE, Flying Fish, TenOneTen Ventures, Leadout Capital, and Wedbush Ventures. The financing includes the conversion of $6 million in Simple Agreements for Future Equity (SAFEs) from earlier pre-seed financing, bringing Meadow AI’s total funding to date to $13 million.

Meadow AI develops an artificial intelligence “co-manager” platform that gives operators real-time visibility into physical locations. The software ingests video and audio feeds alongside labor and inventory data to continuously monitor team execution, service speed, and overall store conditions.

Dubbed a “digital secret shopper,” the technology flags bottlenecks and delivers live prompts and coaching to frontline employees while customers are still on-site. It also automates repetitive administrative tasks, freeing up managers to stay on the floor.

Founded in 2023, Meadow AI was launched by repeat entrepreneurs Max Jai Sim and Abbas Guvenilir alongside CTO Dragos Velicanu. Sim and Guvenilir previously co-founded real estate technology startup Modus, which raised $14 million before being acquired by Compass in 2020, while Guvenilir went on to lead AI and engineering teams at Nordstrom. Velicanu holds a Ph.D. in physics from MIT, where he analyzed particle physics data at CERN, and previously led engineering at Dave AI.

The startup aims to eliminate a persistent blind spot for brick-and-mortar businesses, which lack the deep customer journey analytics available to e-commerce sites. While traditional point-of-sale systems track what was bought, Meadow’s technology reveals why a customer had a poor experience — such as waiting too long in line or going ungreeted.

“Physical businesses generate an enormous amount of information, but most operators still don’t have a clear, real-time understanding of what’s happening across their locations,” Velicanu said in a news release. “We’re trying to make the physical world as understandable and actionable as the digital world.”

Meadow AI says its software grew by 6x over the past year and projects another 5x growth over the next 12 months. The platform has expanded to more than nine brands across the restaurant, retail, hospitality, and entertainment sectors, generating over $3 million in contracted annual recurring revenue and more than $1.4 million in live ARR.

Alongside the funding, Meadow AI announced that former Toast VP of Enterprise Solutions Tanvir Bhangoo has joined as chief revenue officer to oversee enterprise expansion across restaurant and retail accounts.

Meadow AI has grown to 17 employees and is hiring, with plans to use the new capital to expand its engineering, product, and go-to-market teams.

₹11,111 for a meal. And that’s before taxes and beverages. Now that’s a number designed to raise an eyebrow.

But at RAGA, Chef Gaggan Anand’s first restaurant in India, you soon realise that this is not just another expensive tasting menu where you leave wondering where the next meal is coming from. This is a 22 course experience, and by the time you reach the end, you certainly won’t be looking for something else to eat.

Unstated luxury

The first impression is understated luxury. With an extra high ceiling and the kitchen spread across two floors, RAGA is as much a showcase of precision and craftsmanship as it is a restaurant.

There is a stunning open kitchen with some of the finest equipment, handcrafted Japanese crockery, Schott Zwiesel glasses and a kitchen and service team whose strength actually exceeds the restaurant’s seating capacity of just 32 guests.

A chef curated PDR is also expected to open soon, promising an even more personalised experience.

But the real theatre begins when the food arrives.

Gaggan’s cooking is not about simply making familiar Indian flavours taste better. It is about making you question what you are eating, how it was made and sometimes even what you thought you knew about it.

There is a cucumber preparation cut so impossibly thin that it almost disappears into a delicate gel that tastes remarkably like mint chutney. Another creation looks like something entirely unfamiliar, only to explode on the palate with the unmistakable flavour of Indian murmure.

There is nahari. Kashmiri tabak maaz. Modern chaat. Each appears in a form you may never have imagined.

And then comes the brain pepper fry. Except, given its flavour, texture and presentation, many diners may not guess that this apparently indulgent dish is actually vegetarian.

And yes, there is literally a course where you are expected to lick the plate.

That says something about the restaurant. RAGA isn’t afraid to have fun.

Yet it is the techniques, precision and presentation that make you understand why Gaggan Anand has consistently been regarded among the world’s finest chefs. Every course has a purpose. Every texture is considered. Every element has been thought through.

Even something as familiar as chicken wings gets a Gaggan treatment. A small rope is attached to the end so you can pick them up without getting your hands dirty.

Or take the very Indian matar. Even the peas have been painstakingly peeled, with the outer skin removed so that you get to the sweeter layer inside. It is an almost obsessive level of detailing, and this is precisely where you understand why RAGA needs such a large kitchen and service team for just 32 diners.

It is these little details that make the experience memorable.

RAGA is more than Gaggan

The name itself is a portmanteau.

RA comes from Rydo Anton, who is spearheading the restaurant in India, while GA stands for Gaggan Anand, the chef mentor whose vision shapes RAGA.

Joining them is Zorawar Kalra, one of the most influential names in Indian hospitality, whose concepts over the years have played an important role in shaping the contemporary Indian restaurant landscape.

Together, they have created something that feels less like an overseas chef opening a restaurant in India and more like a homecoming.

And perhaps that is what makes RAGA particularly exciting.

India’s restaurant scene has never had it this good. From Nisaba to Indian Accent and Comorin, and now RAGA, Indian cuisine is being interpreted with imagination, confidence and a global sensibility.

Will you get a reservation?

Absolutely not easily.

At least not in the initial months.

With just 32 seats and the curiosity surrounding Gaggan’s first Indian restaurant, reservations are bound to be fiercely sought after.

But the bigger question is whether RAGA will survive beyond the initial excitement.

My answer is yes. And not just survive. I believe it will flourish.

RAGA has the potential to become a destination restaurant for luxury travellers coming to India, particularly those who have experienced Gaggan’s restaurants overseas and faced months of waiting for a table.

And perhaps its biggest contribution will be inspiring more chefs and restaurateurs to think bigger about what Indian food can be.

At ₹11,111 plus taxes and beverages, RAGA certainly isn’t an everyday meal.

But then, this isn’t an everyday restaurant either.

Every course is a revelation. Every plate tells a story. And the experience is worth having at least once.

Address: RAGA, 21A, Janpath Road, Connaught Place, next to Le Meridien, Delhi

Reservations: ragabygaggan.com