Welcome back, my aspiring cyberwarriors!

Many aspiring cyberwarriors write to me asking where they should start in artificial intelligence for cybersecurity and the answer is simple, Hackers-Arise! We have dozens of tutorials–and now classes– on how to apply AI to cybersecurity. In addition, we are the sponsor of the upcoming Wittgenstein Award for the best AI cybersecurity agents. This will give our students an inside look at the development of the best of the best in AI cybersecurity as our students will have an opportunity participate and use the models and agents we develop.

Beyond learning AI for cybersecurity, there is another issue. There are many platforms, models, and hardware to choose from. Comparable to Cisco at the advent of internet in the 1990’s, those who hitched their wagon to Cisco found themselves in an advantageous position regarding jobs and promotions. I want to make the case that NVIDIA is the company you should be hitching your wagon to in this new era.

As you know, NVIDIA is the most valuable company in the world! It is rapidly growing an eco-system that will exceed that of Apple and Cisco. They have quietly built an eco-system of AI that will make it very hard to dislodge them from this dominant position. Jensen Huang and NVIDIA are building an almost impenetrable wall around their eco-system assuring it will be here for years to come.

NVIDIA began as a start-up 1993 building graphics processing units (GPU) for PC gamers. Processing pixels for any graphics intensive product is very compute intensive and NVIDIA made those games come alive. Graphics processing is compute intensive as every image is made of millions of tiny polygons that the GPU must compute it’s size, color, and movement. This means crunching a vast amount of data and Jensen Huang and his colleagues developed a graphics card capable of doing all those calculations very fast through massive parallelism. GPU’s have thousands of cores capable of doing these calculations serially and simultaneously. That is the magic of NVIDIA GPU’s and it is what makes NVIDIA GPU’s the preferred chip for AI. Neural networks–the foundation of our LLM’s at this moment– are built almost entirely from matrix multiplications. This means that the same calculation needs to run over and over on different data. The NVIDIA GPU is uniquely designed for this.

Now let’s take a look at the NVIDIA eco-system that Jensen Huang is building in AI.

Major Equity Investments / Strategic Partnerships

Jensen Huang has made numerous investments in companies positioned to benefit from the coming age of AI, including:

Mellonox –in 2019 NVIDIA agrred to buy Mellanox, an Israeli maker of high-speed Infiniband and Ethernet interconnects for $6.9 billion. NVIDIA needed faster interconnects between to communicate to and from it’s super fast GPU’s and other hardware and Mellanox provided that.

ARM— the British chip designer was the next firm in NVIDIA’s cross-hairs. Jensen Huand recognized that needed powerful and efficient CPU’s to manage his systems. ARM designs RISC-based CPU’s that power the mobile world due to their unique combination of speed and efficiency. NVIDIA offered $40 billion to purchase ARM for what Huang called “the world’s premier computing company for the age of AI.” The US FTC sued to block the acquisition and NVIDIA dropped it’s pursuit of owning ARM. Instead, it holds ARM and it’s CPU’s in close partnership integrating their CPU’s in a multitude of products. Interestingly, ARM is now worth about $250 billion, 6x what Huang offered for it just 6 years ago.

OpenAI — NVIDIA and OpenAI announced a letter of intent to deploy at least 10 gigawatts of NVIDIA systems, with NVIDIA intending to invest up to $100 billion in OpenAI progressively as each gigawatt is deployed. Earlier in 2026, OpenAI raised $110 billion at a $730 billion pre-money valuation, with NVIDIA and SoftBank each investing $30 billion and Amazon investing $50 billion. NVIDIA also noted in its 10-K ( a type of disclosure required by US regulators at the SEC) that it’s finalizing an investment and partnership agreement with OpenAI, though there’s no assurance the transaction will be completed.

Anthropic — NVIDIA and Anthropic announced a deep technology partnership to optimize Claude models for NVIDIA architecture and vice versa; Anthropic’s Series H in May 2026 raised $65 billion at a $965 billion post-money valuation, making it one of NVIDIA’s two largest single-company bets alongside OpenAI.

CoreWeave — NVIDIA holds a stake with an original 7% stake (24.2 million shares) worth roughly $2 billion at IPO, plus an additional $2 billion investment in early 2026, on top of a prior $6.3 billion agreement to purchase CoreWeave’s unused computing capacity through 2032.

xAI — A structure of $7.5 billion in equity plus $12.5 billion in debt, largely through a special purpose vehicle for GPU purchases, supporting xAI’s Colossus 2 data center in Memphis.

Hugging Face — A pending acquisition-related investment of $12.9 billion.

Mistral AI — NVIDIA remains an investor alongside lead backer ASML, with Mistral valued at €11.7 billion (about $13.8 billion).

AI Infrastructure Financing

In August of this year (2026), NVIDIA announced a partnership with some of the largest financial firms in the world including Apollo, BlackRock, Brookfield, Goldman Sachs, and KKR. This partnership was designed to facilitate financing of AI infrastructure and, of course, NVIDIA GPU’s.

Venture / Ecosystem Programs

A roughly £2 billion (~$2.6 billion) UK commitment flowing through partner VCs — Accel, Air Street Capital, Balderton, Hoxton Ventures, and Phoenix Court — into startups in London, Oxford, Cambridge, and Manchester.

Similar “VC Alliance” partnerships extended to European firms including Accel, Elaia, Partech, and Sofinnova, offering DGX Cloud Lepton marketplace credits to portfolio companies.

Scale

NVIDIA has committed over $50 billion across AI labs, cloud services, data centers, and optical communications, with private company assets reaching $47.9 billion by July 2026 and about $18 billion in equity commitments still to be executed.

This list isn’t exhaustive — NVIDIA also has long-standing commercial partnerships with cloud providers (AWS, Microsoft Azure, Google Cloud, Oracle), automakers, and chip/hardware partners that function differently from these financial stakes. Let me know if you’d like me to dig into any particular category.

Summary

NVIDIA and Jensen Huang have quietly built an almost impenetrable eco-system of artificial intelligence systems through acquisitions, partnerships, and financing. Similar to the eco-system CISCO built with networking equipment at the advent of the Internet, it will be advantageous to become part of this eco-system as it will likely be dominant for the foreseeable future.

The post The NVIDIA AI Ecosystem: A Quick Guide first appeared on Hackers Arise.

Major chipmakers announced patches for vulnerabilities recently discovered in their products.

The post Chipmaker Patch Tuesday: Nvidia, AMD, Arm Issue Security Advisories appeared first on SecurityWeek.

Welcome back, aspiring cyberwarriors!

The modern digital ecosystem has undergone a silent but total transformation. Every day, we interact with ARM-based processors billions of times. These chips drive almost all iOS and Android devices and are key to the significant performance improvements seen in Apple’s M-series Macs. Some lightweight notebooks, such as Chromebooks, use ARM processors. IoT devices are largely powered by ARM. Besides that, recently ARM expanded into silicon production with the Arm AGI CPU, its first production-ready silicon designed for agentic AI workloads in data centers. With this level of ubiquity in our digital world, it’s important to be familiar with ARM.

Therefore, this article serves as a foundation for learning about ARM. It delves into the architecture of ARM CPUs, covering design principles and energy efficiency. Let’s get rolling!

What is ARM?

ARM is a family of CPU designs based on a simple, efficient instruction set (RISC). It started as ‘Acorn RISC Machine’, then ‘Advanced RISC Machines’, and now it’s just called ARM.

Unlike traditional chipmakers, Arm Holdings does not manufacture physical processors. Instead, the company designs the foundational CPU architecture and licenses its intellectual property and processor cores to other hardware manufacturers (such as Apple and Nvidia).

What is an ARM-Based CPU?

ARM CPUs use a simple, efficient RISC instruction set. RISC stands for Reduced Instruction Set Computer. It represents a hardware design philosophy focused on streamlining how a processor interprets and executes software instructions.

This design philosophy stands in direct contrast to CISC (Complex Instruction Set Computer), which is the architecture utilized by traditional Intel and AMD x86 processors.

The RISC concept originated in the early 1980s, heavily influenced by research at the University of California, Berkeley. Researchers evaluating resource usage discovered that most software programs only utilized a small fraction of a processor’s complex, built-in instruction set. They realized that if they removed the highly complex, rarely used, and difficult-to-implement instructions, the remaining simpler instructions could execute much faster, while requiring significantly less physical space and power on the silicon chip. This discovery led directly to the development of early RISC designs, including the foundational Acorn RISC Machine (ARM) project in 1983.

Core Principles of RISC Design

RISC architectures use a fixed instruction width for high-speed execution. Unlike CISC architectures that have instructions of varying lengths, a modern 64-bit RISC architecture like ARM64 uses a uniform instruction size, typically 32 bits. This consistency makes it easier for the processor to identify where one instruction ends and the next starts, which helps in quickly fetching, decoding, and executing instructions.

A key feature of RISC design is its Load-Store architecture. In traditional CISC, a single instruction might perform operations directly on data in memory. In RISC, memory access and calculations are separate. In a RISC CPU, Arithmetic Logic Unit (ALU) operations only happen between registers, which are small, fast storage spaces on the processor. To work with data from memory, the processor has to first load it from RAM into a register, perform the calculation in the register, and then store the result back to memory.

To meet the needs of this Load-Store model, RISC processors have a large, uniform register file. Since data cannot be processed directly in memory, the CPU needs many registers to keep temporary data readily available. A 64-bit RISC processor usually has 31 general-purpose 64-bit registers that act as a quick local workspace.

The clear and register-focused design leads to mostly single-cycle execution and effective hardware pipelining. Because RISC instructions are straightforward and mainly work with registers, most can finish in one clock cycle. This single-cycle capability enables the processor to use an instruction pipeline. In this system, while one instruction is executed, another is decoded, and a third is fetched from memory simultaneously. This overlap helps the processor complete a new instruction nearly every clock tick, maximizing efficiency.

Feature / Approach	CISC (e.g., x86)	RISC (e.g., ARM)
Instruction complexity	Single instructions perform multiple tasks (data manipulation, memory access, arithmetic)	Breaks tasks into multiple simpler instructions
Execution example	One instruction: load → compute → store	Three separate instructions: load → compute → store
Decoding logic	Intricate and complex	Simpler, more uniform
Clock cycles per instruction	Often multiple cycles	Usually one cycle per simple instruction
Hardware requirements	Substantial hardware for decoding and execution management	Less hardware for decoding, more uniform control logic
Power & design impact	Higher power consumption and design complexity	Lower power consumption, simpler design
Optimization	Harder to optimize individual operations	Easier to optimize each step independently
Parallel execution	More difficult	Easier to achieve

Energy Efficiency

Firstly, at the core of the RISC philosophy is the use of a smaller vocabulary of simpler, fixed-length instructions. Because the CPU does not have to parse highly complex, variable-length instructions, the physical hardware required to decode and execute instructions is dramatically simplified. This simplicity results in a vastly reduced transistor count. For example, early ARM cores required only 30,000 to 35,000 transistors. Fewer transistors mean that fewer components are active during each instruction cycle, which directly lowers dynamic power consumption and dynamic leakage.

Secondly, RISC processors are designed to scale their power draw dynamically based on the active workload. Through techniques like Dynamic Voltage and Frequency Scaling (DVFS), the processor automatically lowers its operating voltage and clock speed during periods of low computational demand, conserving energy when peak performance is unnecessary. For example, microcontroller-class processors like the ARM Cortex-M series are engineered to draw almost zero power when in deep sleep states, yet they can wake up and execute tasks rapidly on demand.

Thirdly, on a system-on-chip level, modern RISC implementations leverage heterogeneous processing, such as Arm big.LITTLE and DynamIQ technologies. Instead of running all tasks on identical, power-hungry cores, the processor combines:

LITTLE cores: Tiny, ultra-efficient cores optimized to handle routine, low-intensity background tasks (like texting, email, or playing music) using minimal power.

big cores: High-performance cores designed to tackle heavy, sustained workloads (like mobile gaming or intense web browsing).

This dynamic, on-demand task allocation ensures that the high-power “big” cores are only activated when strictly necessary, maximizing overall battery life.

Apple M-series Chips

The Apple M-series chips are a group of processors made by Apple Inc. They are designed for efficient performance and are based on ARM architecture. Each chip includes a CPU, GPU, a Neural Engine for machine learning, and a unified memory system that helps improve overall efficiency.

Apple announced its move to its own M-series chips at the Worldwide Developers Conference (WWDC) on June 22, 2020. This change was from Intel’s x86 processors to ARM-based designs for better power efficiency and performance.

For example, the M1 chip offers up to 3.5 times faster CPU performance while consuming less power than Intel chips for certain tasks. This allows for high performance without generating too much heat.

The M-series chips also improve battery life. Devices often run up to 1.5 times longer than Intel-based Macs. This is due to their optimized power management. In real-world use, like watching videos or doing light work, the MacBook Air can last 15 to 18 hours, compared to the 11 to 12 hours typical of similar Intel models.

By 2026, devices like the Mac Studio and Mac Mini are using M-series CPUs to run advanced AI models directly on users’ desks. Many people are shifting away from paying for AI services and choosing local systems instead.

Summary

In this article, we discussed ARM, a CPU architecture based on RISC principles, which emphasizes simplicity and efficiency. We explained how ARM differs from x86/CISC (Intel/AMD), noting that its smaller instruction set uses fewer transistors and less power. Additionally, we looked at how ARM has impacted Apple’s M-series chips, showing gains in performance, heat management, and battery life, along with the shift toward handling AI tasks on ARM hardware.

The post ARM CPU Architecture: The Power of Simplicity and Efficiency first appeared on Hackers Arise.

Clucky's new alarm app has an option where users are woken up to the sound of a rooster. They then complete a mission to turn it off.

Sometimes regarded as a less violent form of tennis, badminton is still a pretty challenging sport. One which suffers like so many sports from requiring at least two players since magically flying balls and shuttlecocks haven’t been invented yet. After years of tinkering on a shuttlecock serving robot, [Travis Mitchell] hit upon the idea to convert a small industrial robotic arm for the purpose.

The target of this conversion is a positively cute-sized Denso VS050 robotic arm, with Denso helpfully providing a 3D model of the arm as a solid jumping-off point in a CAD project. Here the task of the robotic arm is two-fold: one is to grab a fresh shuttlecock from a hopper with a pneumatic grabber, the other is to feed it into the spinning wheels that grip and launch it. Fortunately [Travis] has a pretty tricked-out workshop available, including the ability to 3D print metal parts, making building the prototype a snap.

After initially thinking of using a Raspberry Pi Pico, he ended up using an ATmega AVR due to the input-output requirements when communicating with the arm. Using a height-adjustable desk as the base, the whole assembly was put together for some testing on the badminton court.

With most of the testing having been done in the shop already, the remaining issue was to determine the best disc material, as the two high-speed discs that grip the shuttlecock must be well-balanced and not stretch too much. Ultimately a 3D printed plastic disc with a silicone strip as gripping surface was found to work pretty well, allowing for the robot to finally start serving its function.

As children, many of us looked wistfully into the cockpits of heavy machinery, wondering just how the series of knobs and levers would do something like operate a bulldozer, crane, or excavator. The nature of these myriad of hydraulic and electronic controls for equipment like this is often inscrutable to adults as well; it takes a considerable amount of training to be able to competently operate most of these machines. But this new controller from MIT may help shorten that training time.

The controller is specifically meant for excavators. In a standard excavator, a pair of joysticks is typically used, with one controlling the swing and the boom and the other controlling the stick and the bucket. Getting used to this combination can take practice, so instead the group of researchers replaced them with a model excavator arm that the operator controls directly with their own arm. The new controller is more intuitive to use as it translates the movements of the model to that of either a real excavator or a training simulation.

The researchers plan to include haptic feedback in future versions, which will hopefully further increase the ease of which new operators can get a feel for using these machines. For those not working towards a new career or an ambitious weekend with rental equipment, there are some other ways of learning how to operate excavators and other pieces of heavy machinery.

Fully autonomous space mission operations require the ability to detect faults and compensate for them without human intervention. To address this challenge and provide model-based support for system design and operations, it is important to connect fault management (FM) and model-based systems engineering (MBSE). This approach was successfully demonstrated with the model-based generation of a failure modes and effects analysis and fault trees using NASA’s HelioSwarm mission early design information.

As NASA strives to push the boundaries of space travel with the Artemis program and the agency’s upcoming deep-space science missions, increased system autonomy and resiliency have inevitably become key technology needs. Autonomous operations require fault management (FM) software to detect issues that occur in space so they can be mitigated automatically without human intervention. Designing autonomous missions requires a multi-disciplinary approach that connects FM with the model-based systems engineering (MBSE) approach used in mission design to ensure that resilient, fault-tolerant systems are architected, modeled, and integrated during the design phase.

To address this need, NASA awarded a Phase II Small Business Innovation Research (SBIR) contract to Qualtech Systems Inc. (QSI) for development of FM capabilities and enhancements to its commercially available toolset, TEAMS® (a product that resulted from commercialization of the company’s earlier NASA-sponsored SBIR work), to support HelioSwarm and other NASA heliophysics missions.

The QSI Approach

One of the most important tasks in this effort was to connect system health management (SHM) and FM to the systems engineering (SE) process. Together, SHM/FM consists of a set of mechanisms that ensure that mission goals are achieved by preventing failures from occurring, or detecting and then mitigating them if they do occur. The SE process coordinates, cross-checks, and integrates system elements to achieve mission goals and is integral during the design, specification, and verification and validation (V&V) of systems. NASA often employs a model-based approach for its SE process, using Systems Modeling Language (SysML) as the framework.

Despite their inherently close relationship to SE in practice, SHM/FM practices have typically not been tightly integrated with SE. Often, SHM/FM is incorporated only after a nominal system is designed, which essentially makes SHM/FM a bandage fix for problems after they occur, without considering how issues might have been prevented. In addition, SE and SHM/FM often involve separate sets of subject matter experts with stove-piped knowledge repositories. This situation can lead to use of modeling methodologies and analyses processes that yield inconsistent results, and can potentially result in inefficiencies throughout the mission life cycle.

This NASA-funded QSI team’s approach integrates SHM/FM directly within the MBSE process from the beginning of a project. This method enables the FM design to be evaluated in an operational context by showing how the SHM/FM schemes mitigate the effects of simulated component-level physical and functional failures. This technique also facilitates trade studies to evaluate the merits of various FM architectures during the design phase.

Under this SBIR effort, QSI worked with the SysML v2 Submission Team (SST) — an assorted group of end users, vendors, academics, and government liaisons involved in the development of specifications for SysML v2, which is the latest iteration of SysML. The QSI team incorporated FM concepts and modeling standards into SysML v2, then they demonstrated how SysML v2 models could translate to the failure space models produced by the QSI toolset.

This capability enables systems engineers to use QSI’s commercial modeling tool set andanalyze the FM aspects of a system design captured in SysML v2. By capturing the causes and impacts of failures, QSI’s toolset enables mission designers to perform Fault Modes, Effects, and Criticality Analyses (FMECAs) and Fault Tree Analyses (FTAs) to analyze, quantify, and improve the diagnostics and availability of the system. Furthermore, the toolset recommends design improvements (e.g., optimal location of sensors onboard the spacecraft) based on the results from such analyses, and it provides these recommendations in industry-standard formats that can be easily understood and incorporated into the design.

During this SBIR effort, theQSI toolset was also enhanced to interface with an MBSE framework and facilitate the creation, evaluation, and selection of FM concepts for a mission design. The toolset now enables FM concepts to be tested early in the design process so that adequate detection and diagnosis can be built into the system design, which could potentially lower the total cost of development, facilitate enhanced communication and coordination among mission team members, and reduce development risks (cost and schedule).

The HelioSwarm Demonstration

HelioSwarm will transform our understanding of turbulence in the solar wind and the connected Sun–Earth system. The mission uses a constellation, or “swarm,” of one hub and eight co-orbiting small satellites to make the first simultaneous, multiscale measurements of magnetic-field fluctuations and proton flows in the dynamic cislunar space environment. Because plasma turbulence transfers energy across many scales, from fluid-scale motions to kinetic-scale particle dynamics, it cannot be fully understood from a single measurement point, or from measurements at only a single scale. HelioSwarm’s spacecraft will fly with separations ranging from tens to thousands of kilometers, allowing scientists to reconstruct the three-dimensional structure and dynamics of turbulent space plasma. These observations will reveal how energy moves through the solar wind, transforming our understanding of fundamental plasma processes that operate near Earth, around the Sun, and throughout the universe.

Plasma turbulence is the process by which energy contained in fluctuating magnetic fields and plasma motion cascades from large to smaller spatial scales. When the cascade approaches small spatial scales associated with kinetic dissipation, the energy transfers into particle heat. Without turbulent cascades in space plasmas, most of the universe would be far colder than observed. Because of the fundamental thermodynamic role it plays in fluids, including space plasmas, many contend that turbulent fluids are the most important unsolved problem in classical physics.

The QSI team created a SysML v2 design model of HelioSwarm subsystems and top-level mission requirements, capturing the flowdown from mission goals to the design. The team then used its enhanced toolset to translate the HelioSwarm SysML v2 model into an FM model. The HelioSwarm models consist of key subsystems of the hub spacecraft and eight node satellites, including subsystems for command and data handling; electric power; attitude control; propulsion, thermal, and separation hardware payload sensors; and ground and space communications. Using the QSI toolset, mission designers then generated FMECAs and FTAs that were translated into a standardized SysML report. Furthermore, these FM analyses generated recommendations (e.g., for sensor placement) that were provided as proposed updates to the system design. This process will support the design of small spacecraft swarms with inherent redundancy to enhance science observations and other NASA goals, such as providing mission support for lunar surface operations.

Relevance to future NASA missions and non-NASA applications

The technology developed via this latest SBIR effort could be of high value for future NASA missions — especially those that require autonomous operation. The QSI TEAMS® toolset was baselined for Vehicle Systems Management functions on NASA’s Gateway project and retains applicability to future human-rated spacecraft. System design engineers could use this technology to incorporate fault mitigation strategies to improve design with additional insight into the overall system resilience — right at the beginning of the design phase.

This technology may also have applications outside of NASA. Comprehensive and efficient FM analyses and architecture trade studies are of critical importance to complex and high-value military systems such as aircraft, surface ships, submarines, and even modern ground-fighting vehicles. Additionally, this technology could be applicable to emerging commercial space systems, civilian aircraft and maritime systems, transportation, and power generation and distribution equipment.
 
For additional details about this effort, see the relevant TechPort entries: here, here, and here.
Project Lead(s): Dr. Sudipto Ghoshal, Mr. Deepak Haste, Qualtech Systems, Inc.
Sponsoring Organization(s): NASA Ames Research Center

Jen combines flowers and summer harvests from her Connecticut flower farm into colorful, seasonal arrangements